1. Field of the Invention
The present invention relates to a clock compensation device of the semiconductor circuit, and more particularly, to a Delay Locked Loop device which is type of the clock compensation devices generating an internal clock by receiving an external clock.
2. Description of the Prior Art
Delay Locked Loop device generates an internal clock by receiving an external clock. It is utilized to match the frequency and the phase of the external clock and the internal clock.
In general, Delay Locked Loop device includes a phase detector, a charge pump and a delay means. The phase detector compares and detects the difference of frequency or the difference of the phase of the external clock and the internal clock. The charge pump which receives the output signal from the phase detector and outputs the pumping signal controls the delay time of the delay means by controlling delay elements in the delay means. The delay means is controlled by the output signal from the charge pump and outputs the internal clock by receiving the output clock.
FIG. 1 is a block diagram of a Delay Locked Loop device of a prior art. Delay Locked Loop device in FIG. 1 further includes a filter to eliminate noises in the output signal from the charge pump.
FIG. 2 is a detailed circuit of a delay means in FIG. 1. The delay means includes a plurality of delay elements. As described above, the delay means generates an internal clock by receiving an external clock. The phase difference and the frequency difference between the internal and external clock are controlled by the pump voltage Vpump from the charge pump.
In other words, when an external clock is inputted, the delay means generates a certain internal clock when the pump voltage Vpump maintains an arbitrary voltage level.
Thereafter, the phase detector compares and detects the frequency and/or phase of the external and internal clock.
If the frequencies and/or phases of the two clocks matchs, charge pump maintains the initial pump voltage Vpump and the phase detector outputs no signal.
However, if the frequencies and/or phases of the two clocks does not match, the phase detector generates an output signal to control charge pump. Then, the charge pump outputs a controlled pump voltage Vpump. The voltage level of the controlled pump voltage Vpump increases or decreases in accordance with the state of the output signal from the phase detector.
For example, if the phase of the internal clock outputted from the delay means lags more than the phase of the external clock, the phase detector outputs high voltage level to raise the level of the pump voltage Vpump from the charge pump to compensate the lag in the internal clock.
The increase in pump voltage Vpump is inputted to the bias transistors of the delay elements, which consist of CMOS transistors, to shorten the delay time. Accordingly, the lag phase of the internal clock is compensated. If the phase of the internal clock is faster, then the phase detector compares the difference of two phases and outputs low voltage level to decrease the level of the pump voltage Vpump from the charge pump to compensate the faster phase of the internal clock.
Accordingly, if such a control process for the phase continues repeatedly, the Delay Locked Loop device arrives at the Lock state.
Wherein, the Lock state indicates that the frequencies and/or phases of the external clock and internal clock match.
As illustrated above, the Delay Locked Loop device controls the delay time by controlling the bias transistors in the delay elements.
However, the pump voltage level changes slowly because the output signal from the charge pump is an analog signal. For this reason, the delay time of the Delay Locked Loop device also changes slowly. Accordingly, very long Lock time is required in order to match frequencies and/or phases between the external clock and internal clock. In addition, there is a problem wherein, the frequency bandwidth of the Delay Locked Loop device in a prior art is confined to certain range because the entire delay time of the delay means is fixed.
Therefore, it is an object of the invention to provide a Delay Locked Loop device which improves the locking time and extends the operating frequency bandwidth.
Another object of the invention is to provide a Delay Locked Loop device which includes a plurality of the delay elements each of which outputs different delay times.
Still, another object of the invention is to provide a Delay Locked Loop device which includes a phase detector for detecting the phase difference, and includes counter for selecting one of the output signals from the delay elements.